The present invention relates generally to a semiconductor memory device and a method of manufacturing the semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device in which resistance of source or drain diffusion layer can be effectively reduced and size of each memory cell can be reduced, and a method of manufacturing such memory device wherein number of process steps can be decreased to simplify manufacturing process of the memory device.
In order to reduce resistance of a diffusion layer of a bit line or a source line of a semiconductor memory device, such as a flash memory device, there is known a method in which a metal layer is formed on the diffusion layer. Especially, with respect to the flash memory device having conductors or wirings each composed of a buried diffusion layer, three methods are considered to form the metal layer on the conductors. In the first method, a metal layer or a metal compound layer is formed on whole surface of a substrate, and thereafter unnecessary portions of the metal layer or the metal compound layer are removed by using a photolithography process and an etching process. In the second method, by using a salicidation (self-aligned silicidation), a titanium layer contacting a silicon layer or substrate is silicided to form titanium silicide layer. In the third method, a tungsten layer, for example, is grown as the metal layer, by using selective CVD.
However, when the salicidation of titanium is used as in the second method, there is a problem that titanium coagulates or coheres in the titanium silicide layer when oxidation is performed thereafter. Also, in the third method, when selective growth of tungsten is used, it is necessary to form a barrier metal layer between the conductors composed of the buried diffusion layer and the tungsten layer and to process the barrier metal layer by using process steps similar to those used in the first method. Therefore, conventionally, the first method had to be used to form the metal layer on the buried diffusion layer.
FIGS. 5A and 5B illustrates a structure of a flash memory device fabricated by using a prior art method, that is, the first method mentioned above. FIG. 5A is a plan view of the flash memory device, and FIG. 5B is a cross sectional view taken along the line Axe2x80x94A of FIG. 5A.
As shown in FIG. 5A, a plurality of control gate conductors 39 which also constitute word lines are disposed in a lateral direction in the drawing. Under the control gate conductors 39, a source region 30 and a drain region 31 each made of a buried diffusion layer are formed in a vertical direction via an interlayer oxide film 37 and so on. The drain region 31 also functions as a bit line.
As shown in FIG. 5B, on a channel region between the source region 30 and the drain region 31, a tunnel oxide film 34, a floating gate 35, an ONO film (oxide film-nitride film-oxide film) 38, and the control gate 39 are formed sequentially from the bottom. In order to reduce the resistance of each of the conductors of the buried diffusion layer, a titanium nitride layer 36 is formed as a metal layer or a metallic compound layer on the surface of each of the source region 30 and the drain region 31. On the side surfaces of the floating gate 35, oxide film sidewall spacers 33 are formed and isolate the floating gate 35 and the titanium nitride layer 36 from each other. The titanium nitride layer 36 also extends from the surface of each of the source region 30 and the drain region 31 along the side surface of the sidewall spacers 33.
With reference to FIGS. 6A through 6D, explanation will be made on a method of manufacturing the conventional flash memory device shown in FIGS. 5A and 5B.
First, as shown in FIG. 6A, a semiconductor substrate 29 in which element isolation regions 32 having a structure such as STI (Shallow Trench Isolation) and a tunnel oxide film 34 are formed is prepared. On the semiconductor substrate 29, a polycrystalline silicon (polysilicon) layer is formed by using, for example, CVD (Chemical Vapor Deposition). The polysilicon layer is patterned by using a photolithography process such that a floating gate 35 made of polysilicon is disposed in the direction of the bit line. Further, a silicon oxide film is formed on whole surface of the semiconductor substrate and the silicon oxide film is etched back by anisotropic etching, so that oxide film sidewall spacers 33 are formed on the side surface of the floating gate 35. Thereafter, buried diffusion layers of the source 30 and the drain 31 are formed by ion implantation.
Then, as shown in FIG. 6B, high refractory metal or metal compound, for example, titanium nitride in this case, is sputtered on whole surface of the semiconductor substrate to form a titanium nitride layer 40.
Further, as shown in FIG. 6C, the titanium nitride layer 40 is patterned by using a photolithography process and an etching process such that portions of the titanium nitride layer 40 on the floating gate 35 and on the element isolation region 32 are removed. In this case, as shown in FIG. 6C, it is required that both ends of each of the remained titanium nitride layers 40 are on the oxide film sidewall spacer 33 and on the element isolating region 32. If the titanium nitride layer 40 is patterned such that end portions of the remained titanium nitride layer 40 are on the diffusion layers 30 and 31, the semiconductor substrate 29 including the diffusion layers 30 and 31 is exposed and over-etched by the etching process of patterning the titanium nitride layer 40.
As shown in FIG. 6D, an oxide film is then grown on whole surface of the semiconductor substrate by using, for example, CVD, and this oxide film is etched back to form an interlayer oxide film 37, such that the titanium nitride layers 40 are buried under the interlayer oxide film 37. Thereafter, portion of the oxide film on the floating gate 35 is selectively removed by using a photolithography process and an etching process.
Then, the ONO film 38 and a tungstenpolyside layer for forming a control gate 39 are grown on whole surface of the substrate. Thereafter, patterning of the control gate 39, the ONO film 38 and the floating gate 35 is performed by using a photolithography process and an etching process, and a semiconductor memory device having a configuration shown in FIGS. 5A and 5B is obtained.
The prior art technique described above has the following problems.
In the first problem, when a metal layer such as a titanium nitride layer 36 is formed, a photolithography process is required which adds to the number of process steps to fabricate a memory device. Since the metal layer is selectively formed on the buried diffusion layer, the photolithography process is required.
In the second problem, when a portion of the interlayer oxide film on each of the floating gates is removed, a photolithography process is required which adds to the number of process steps to fabricate a memory device. As shown in FIG. 6C, if each of the metal layer, such as the titanium nitride layer 40, is formed by using a photolithography process and an etching process such that an end portion of the titanium nitride layer 40 comes near the upper end of the oxide film sidewall spacer 33, the top tip portion of the titanium nitride layer 40 protrudes in a direction perpendicular to the substrate 29 from the surface of the portion near the upper end of the oxide film sidewall spacer 33 by the amount corresponding to the thickness of the titanium nitride layer 40, so that the position of the top tip portion of the titanium nitride layer 40 becomes higher than the upper surface of the floating gate 35. If, after forming the oxide film 37 on the floating gate 35, the oxide film 37 is etched back until the floating gate 35 is exposed, a portion of the titanium nitride layer 40 is also exposed. If the ONO film 38 and the control gate 39 are formed under the condition a portion of the titanium nitride layer 40 is exposed, the thickness of the ONO film 38 formed on the top tip portion of the titanium nitride layer 40 becomes thinner than that of other portions, because the top tip portion of the exposed titanium nitride layer 40 is sharp-pointed as can be seen from FIGS. 5 and 6. Therefore, the titanium nitride layer 40 closely opposes to the control gate 39 via the relatively thin portion of the ONO film 38. In such case, if a high potential voltage is applied therebetween in a write operation or in an erase operation, there is a possibility of occurrence of insulation breakdown between the titanium nitride layer 40 and the control gate 39. Also, in this case, if the ONO film 38 is formed thickly to avoid insulation breakdown between the titanium nitride layer 40 and the control gate 39, the ONO film 38 becomes too thick between the control gate 39 and the floating gate 35 and a bad influence may be given on the operation of the flash memory device. In order to expose the top surface of the floating gate 35 and to keep a portion of the oxide film 37 remained on the top tip portion of the titanium nitride layer 40, it is necessary, after etching back the oxide film 37 to a certain extent, to selectively remove only a portion of the oxide film on the floating gate 35 by using a photolithography process, as shown in FIG. 6D. Therefore, the additional photolithography process is required.
In the third problem, it is necessary to increase the width or thickness of each of the sidewall spacers and the length of the floating gate at least by the amount of error margin or registration margin relating to the photolithography process, and therefore it is necessary to increase the size of each memory cell. In other words, since the prior art technique uses photolithography processes to form the metal layer such as the titanium nitride layer 40 and to selectively remove the interlayer oxide 37 on the floating gate 35, it is necessary to reserve registration margin of the photolithography processes, and the size of each memory cell of the semiconductor memory device increases by the amount corresponding to the registration margin.
It is therefore an object of the present invention to improve the drawbacks of the prior art technique mentioned above, and to provide a novel semiconductor memory device and a novel method of manufacturing the semiconductor memory device, wherein the semiconductor memory device can be manufactured easily and precisely.
It is another object of the present invention to provide a novel semiconductor memory device and a novel method of manufacturing the semiconductor memory device, wherein manufacturing process can be simplified by decreasing the number of photolithography processes.
It is another object of the present invention to provide a novel semiconductor memory device and a novel method of manufacturing the semiconductor memory device, wherein registration margin required for the width or thickness of the oxide film sidewall spacers and the length of the floating gate can be removed by decreasing the number of photolithography processes, thereby size of each memory cell can be reduced.
According to an aspect of the present invention, there is provided a semiconductor memory device. The semiconductor memory device comprises: a semiconductor substrate, such as a silicon substrate; element isolation regions formed in said semiconductor substrate; active regions between said element isolation regions; buried diffusion layers each constituting at least a drain region or a source region; floating gates each formed on a channel region between said drain region and said source region via an insulating film; and sidewall spacers formed on side surfaces of said floating gates and made of insulating material. The semiconductor memory device further comprises: a first layer formed on said buried diffusion layers and said sidewall spacers and comprising high refractory metal or metal compound, such as titanium nitride; a second layer formed on said first layer and made of material different from that of said first layer, such as an oxide or tungsten; a third layer formed on said second layer and comprising insulating material, such as an oxide; a fourth layer formed on said floating gate and said third layer and comprising insulating material, such as an oxide or nitride; and a control gate formed on said fourth layer.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device. The method comprises: providing a semiconductor substrate; forming element isolation regions in said semiconductor substrate and defining active regions between said element isolation regions; forming floating gates within said active regions and forming dummy floating gates on said element isolation regions; forming buried diffusion layers each constituting at least a drain region or a source region; and forming sidewall spacers made of insulating material on side surfaces of said floating gates and on side surfaces of said dummy floating gates. The method further comprises; forming a first layer comprising high refractory metal or metal compound, such as titanium nitride on the surface of said substrate; forming a second layer made of a material different from the material of said first layer on said first layer, such as an oxide or tungsten; etching back said second layer to expose portions of said first layer on said floating gate and said dummy floating gate, and leaving a portion of said second layer between said floating gate within said active region and said dummy floating gate on said element isolation region and on said first layer; and etching back said first layer by using the remained portion of said second layer as a mask to expose top surfaces of said floating gate and said dummy floating gate, and leaving a portion of said first layer between said floating gate within said active region and said dummy floating gate on said element isolation region.